View PCF8579T1_4458192.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PCF8579
LCD column driver for dot matrix graphic displays
Rev. 05 -- 11 May 2009 Product data sheet
1. General description
The PCF8579 is a low power CMOS1 LCD column driver, designed to drive dot matrix graphic displays at multiplex rates of 1:8, 1:16, 1:24 or 1:32. The device has 40 outputs and can drive 32 x 40 dots in a 32 row multiplexed LCD. Up to 16 PCF8579s can be cascaded and up to 32 devices may be used on the same I2C-bus (using the two slave addresses). The device is optimized for use with the PCF8578 LCD row/column driver. Together these devices form a general purpose LCD dot matrix driver chip set, capable of driving displays of up to 40960 dots. The PCF8579 is compatible with most microcontrollers and communicates via a two-line bidirectional bus (I2C-bus). To allow partial VDD shutdown the ESD protection system of the SCL and SDA pins does not use a diode connected to VDD. Communication overhead is minimized by a display RAM with auto-incremented addressing and display bank switching.
2. Features
I LCD column driver I Used in conjunction with the PCF8578, this device forms part of a chip set capable of driving up to 40960 dots I 40 column outputs I Selectable multiplex rates; 1:8, 1:16, 1:24 or 1:32 I Externally selectable bias configuration, 5 or 6 levels I Easily cascadable for large applications (up to 32 devices) I 1280-bit RAM for display data storage I Display memory bank switching I Auto-incremented data loading across hardware subaddress boundaries (with PCF8578) I Power-On Reset (POR) blanks display I Logic voltage supply range 2.5 V to 6 V I Maximum LCD supply voltage 9 V I Low power consumption I I2C-bus interface I Compatible with most microcontrollers I Optimized pinning for single plane wiring in multiple device applications (with PCF8578) I Space saving 56-lead small outline package and 64-pin quad flat pack
1.
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 15.
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
3. Applications
I I I I I Automotive information systems Telecommunication systems Point-of-sale terminals Industrial computer terminals Instrumentation
4. Ordering information
Table 1. Ordering information Package Name PCF8579T/1 PCF8579H/1 PCF8579HT/1
[1]
Type number
Description plastic very small outline package; 56 leads plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm[1] plastic thin quad flat package; 64 leads; body 10 x 10 x 1.0 mm
Version SOT190-1 SOT314-2 SOT357-1
VSO56 LQFP64 TQFP64
Should not be used for new designs.
5. Marking
Table 2. Marking codes Marking code PCF8579T PCF8579H PCF8579HT Type number PCF8579T/1 PCF8579H/1 PCF8579HT/1
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
2 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
6. Block diagram
C39 - C0
VDD V3 V4 VLCD COLUMN(1) DRIVERS
PCF8579
TEST VSS Y DECODER AND SENSING AMPLIFIERS
OUTPUT CONTROLLER
32 x 40 BIT DISPLAY RAM
DISPLAY DECODER
POWER-ON RESET
X DECODER
A3 A2 A1 A0
SUBADDRESS COUNTER
RAM DATA POINTER Y X
TIMING GENERATOR
SYNC CLK
SCL SDA
INPUT FILTERS
I2C-BUS CONTROLLER
COMMAND DECODER
msa919
n.c.
SA0
(1) Operates at LCD voltage levels, all other blocks operate at logic levels.
Fig 1.
Block diagram
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
3 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
7. Pinning information
7.1 Pinning
SDA SCL SYNC CLK VSS TEST SA0 A3 A2
1 2 3 4 5 6 7 8 9
56 C0 55 C1 54 C2 53 C3 52 C4 51 C5 50 C6 49 C7 48 C8 47 C9 46 C10 45 C11 44 C12 43 C13 42 C14 41 C15 40 C16 39 C17 38 C18 37 C19 36 C20 35 C21 34 C22 33 C23 32 C24 31 C25 30 C26 29 C27
001aaj888
A1 10 A0 11 VDD 12 n.c. 13 V3 14 V4 15 VLCD 16 C39 17 C38 18 C37 19 C36 20 C35 21 C34 22 C33 23 C32 24 C31 25 C30 26 C29 27 C28 28
PCF8579T
Top view. For mechanical details, see Figure 25.
Fig 2.
Pinning diagram of PCF8579T/1 (VSO56)
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
4 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
60 C10
59 C11
58 C12
57 C13
56 C14
55 C15
54 C16
53 C17
52 C18
51 C19
50 C20
C5 C4 C3 C2 C1 C0 SDA SCL SYNC
1 2 3 4 5 6 7 8 9
49 C21
64 C6
63 C7
62 C8
61 C9
48 C22 47 C23 46 C24 45 C25 44 C26 43 C27 42 C28 41 C29 40 C30 39 C31 38 C32 37 C33 36 C34 35 C35 34 n.c. 33 C36
PCF8579H
CLK 10 VSS 11 TEST 12 SA0 13 A3 14 n.c. 15 A2 16
A1 17
A0 18
n.c. 19
VDD 20
n.c. 21
V3 22
V4 23
VLCD 24
n.c. 25
n.c. 26
n.c. 27
n.c. 28
n.c. 29
C39 30
C38 31
C37 32
001aaj954
Top view. For mechanical details, see Figure 26.
Fig 3.
Pinning diagram of PCF8579H/1 (LQFP64)
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
5 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
60 C10
59 C11
58 C12
57 C13
56 C14
55 C15
54 C16
53 C17
52 C18
51 C19
50 C20
C5 C4 C3 C2 C1 C0 SDA SCL SYNC
1 2 3 4 5 6 7 8 9
49 C21
64 C6
63 C7
62 C8
61 C9
48 C22 47 C23 46 C24 45 C25 44 C26 43 C27 42 C28 41 C29 40 C30 39 C31 38 C32 37 C33 36 C34 35 C35 34 n.c. 33 C36
PCF8579HT
CLK 10 VSS 11 TEST 12 SA0 13 A3 14 n.c. 15 A2 16
A1 17
A0 18
n.c. 19
VDD 20
n.c. 21
V3 22
V4 23
VLCD 24
n.c. 25
n.c. 26
n.c. 27
n.c. 28
n.c. 29
C39 30
C38 31
C37 32
001aaj841
Top view. For mechanical details, see Figure 27.
Fig 4.
Pinning diagram of PCF8579HT/1 (TQFP64)
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
6 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
7.2 Pin description
Table 3. Symbol Pin description Pin VSO56 SDA SCL SYNC CLK VSS TEST[1] SA0 A3 to A0 VDD n.c.[2] V3, V4 VLCD C39 to C0
[1] [2]
Description LQFP64, TQFP64 7 8 9 10 11 12 13 14, 16 to 18 20 I2C-bus serial data input/output I2C-bus serial clock input cascade synchronization output external clock input/output ground test pin I2C-bus slave address input (bit 0) I2C-bus subaddress inputs supply voltage
1 2 3 4 5 6 7 8 to 11 12 13 14, 15 16 17 to 56
15, 19, 21, 25 not connected to 29, 34 22, 23 24 30 to 33, 35 to 64, 1 to 6 LCD bias voltage inputs LCD supply voltage LCD column driver outputs
The TEST pin must be connected to VSS. Do not connect, these pins are reserved.
8. Functional description
The PCF8579 column driver is designed for use with the PCF8578. Together they form a general purpose LCD dot matrix chip set. Typically up to 16 PCF8579s may be used with one PCF8578 (examples of cascading the devices see Table 16, Figure 21, Figure 22, Figure 23 and Figure 24). Each of the PCF8579s is identified by a unique 4-bit hardware subaddress, set by pins A0 to A3. The PCF8578 can operate with up to 32 PCF8579s when using two I2C-bus slave addresses. The two slave addresses are set by the logic level on input SA0.
8.1 Power-on reset
At power-on the PCF8579 resets to a defined starting condition as follows: 1. Display blank (in conjunction with PCF8578) 2. 1:32 multiplex rate 3. Start bank 0 selected 4. Data pointer is set to X, Y address 0, 0 5. Character mode 6. Subaddress counter is set to 0 7. I2C-bus interface is initialized
PCF8579_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
7 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
Remark: Do not transfer data on the I2C-bus for at least 1 ms after power-on to allow the reset action to complete.
8.2 Multiplexed LCD bias generation
The bias levels required to produce maximum contrast depend on the multiplex rate and the LCD threshold voltage (Vth). Vth is typically defined as the RMS voltage at which the LCD exhibits 10 % contrast. Table 4 shows the optimum voltage bias levels and Table 5 the discrimination ratios (D) for the different multiplex rates as functions of Voper. V oper = V DD - V LCD The RMS on-state voltage (Von(RMS)) for the LCD is calculated with the equation V on ( RMS ) =
V oper
(1)
1 n-1 -- + -----------------------n n( n + 1)
(2)
and the RMS off-state voltage (Voff(RMS)) with the equation V off ( RMS ) =
V oper
2( n - 1) -----------------------------n( n + 1 )2
(3)
where the values for n are determined by the multiplex rate (1:n). Valid values for n are: n = 8 for 1:8 multiplex n = 16 for 1:16 multiplex n = 24 for 1:24 multiplex n = 32 for 1:32 multiplex
Table 4. Optimum LCD voltages Multiplex rate 1:8 1:16 0.800 1:24 0.830 1:32 0.850 0.739
Bias ratios
V2 ------------V oper V3 ------------V oper V4 ------------V oper V5 ------------V oper
0.522
0.600
0.661
0.700
0.478
0.400
0.339
0.300
0.261
0.200
0.170
0.150
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
8 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
Discrimination ratios Multiplex rate 1:8 0.297 1:16 0.245 1:24 0.214 1:32 0.193
Table 5.
Discrimination ratios
V off ( RMS ) -----------------------V oper V on ( RMS ) ----------------------V oper V on ( RMS ) D = -----------------------V off ( RMS ) V oper ------------V th
0.430
0.316
0.263
0.230
1.447
1.291
1.230
1.196
3.370
4.080
4.680
5.190
Figure 5 shows the values of Table 4 as graphs.
1.0 Vbias Voper 0.8 V3/Voper 0.6 V4/Voper 0.4 V2/Voper
msa838
V5/Voper 0.2
0
1:8
1:16
1:24 1:32 multiplex rate
Vbias = V2, V3, V4, V5; see Table 4.
Fig 5.
Vbias/Voper as a function of the multiplex rate
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
9 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
8.3 LCD drive mode waveforms
Tfr VDD V2 V3 V4 V5 VLCD VDD V2 V3 V4 V5 VLCD SYNC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 ON OFF
ROW 0
1:8
COLUMN
ROW 0
VDD V2 V3 V4 V5 VLCD VDD V2 V3 V4 V5 VLCD SYNC
1:16
COLUMN
VDD V2 ROW 0 V3 V4 V5 VLCD VDD V2 COLUMN V3 V4 V5 VLCD SYNC
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
1:24
VDD V2 ROW 0 V3 V4 V5 VLCD VDD V2 COLUMN V3 V4 V5 VLCD SYNC
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1:32
msa841
column display
Fig 6.
LCD row and column waveforms
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
10 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
Tfr VDD V2 V3 V4 V5 VLCD VDD V2 V3 V4 V5 VLCD VDD V2 V3 V4 V5 VLCD VDD V2 V3 V4 V5 VLCD
state 1 (OFF) state 2 (ON)
ROW 1 R1 (t)
ROW 2 R2 (t)
dot matrix 1:8 multiplex rate
COL 1 C1 (t)
COL 2 C2 (t)
Voper
0.261 Voper Vstate 1(t) 0V 0.261 Voper
Voper Voper 0.478 Voper 0.261 Voper Vstate 2(t) 0V 0.261 Voper 0.478 Voper Voper
msa840
Vstate1(t) = C1(t) - R1(t).
V on ( RMS ) ---------------------- = V oper
1 8-1 -- + ----------------------- = 0.430 8 8( 8 + 1)
Vstate2(t) = C2(t) - R2(t).
V off ( RMS ) ----------------------- = V oper Fig 7.
2( 8 - 1) ------------------------------ = 0.297 8( 8 + 1 )2
LCD drive mode waveforms for 1:8 multiplex rate
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
11 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
Tfr VDD V2 V3 V4 V5 VLCD VDD V2 V3 V4 V5 VLCD VDD V2 V3 V4 V5 VLCD VDD V2 V3 V4 V5 VLCD Voper 0.2 Voper 0V 0.2 Voper
state 1 (OFF) state 2 (ON)
ROW 1 R1 (t)
ROW 2 R2 (t)
COL 1 C1 (t)
dot matrix 1:16 multiplex rate
COL 2 C2 (t)
Vstate 1(t)
Voper Voper 0.6 Voper Vstate 2(t) 0.2 Voper 0V 0.2 Voper 0.6 Voper Voper
msa836
Vstate1(t) = C1(t) - R1(t).
V on ( RMS ) ---------------------- = V oper
1 16 - 1 ----- + ------------------------------ = 0.316 16 16 ( 16 + 1 ) 2 ( 16 - 1 ) ------------------------------------ = 0.254 16 ( 16 + 1 ) 2
Vstate2(t) = C2(t) - R2(t).
V off ( RMS ) ----------------------- = V oper Fig 8.
LCD drive mode waveform for 1:16 multiplex rate
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
12 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
8.4 Timing generator
The timing generator of the PCF8579 organizes the internal data flow from the RAM to the display drivers. An external synchronization pulse SYNC is received from the PCF8578. This signal maintains the correct timing relationship between cascaded devices.
8.5 Column drivers
Outputs C0 to C39 are column drivers which must be connected to the LCD. Unused outputs should be left open-circuit.
8.6 Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial Data Line (SDA) and a Serial Clock Line (SCL) which must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy.
8.6.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this moment will be interpreted as control signals.
8.6.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH, is defined as the STOP condition (P).
8.6.3 System configuration
A device transmitting a message is a transmitter, a device receiving a message is the receiver. The device that controls the message flow is the master and the devices which are controlled by the master are the slaves.
8.6.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each data byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal the end of a data transmission to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
13 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
SDA
SCL data line stable; data valid change of data allowed
mba607
Fig 9.
Bit transfer
SDA
SCL S START condition P STOP condition
mba608
Fig 10. Definition of START and STOP condition
SDA SCL MASTER TRANSMITTER / RECEIVER SLAVE TRANSMITTER / RECEIVER MASTER TRANSMITTER / RECEIVER
mba605
SLAVE RECEIVER
MASTER TRANSMITTER
Fig 11. System configuration
START condition SCL FROM MASTER 1 2 8
clock pulse for acknowledgement 9
DATA OUTPUT BY TRANSMITTER S DATA OUTPUT BY RECEIVER
mba606
The general characteristics and detailed specification of the I2C-bus are available on request.
Fig 12. Acknowledgement on the I2C-bus
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
14 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
8.6.5 I2C-bus controller
The I2C-bus controller detects the I2C-bus protocol, slave address, commands and display data bytes. It performs the conversion of the data input (serial-to-parallel) and the data output (parallel-to-serial). The PCF8579 acts as an I2C-bus slave transmitter/receiver. Device selection depends on the I2C-bus slave address, the hardware subaddress and the commands transmitted.
8.6.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines.
8.6.7 I2C-bus protocol
Two 7-bit slave addresses (0111100 and 0111101) are reserved for both the PCF8578 and PCF8579. The least significant bit of the slave address is set by connecting input SA0 to either logic 0 (VSS) or logic 1 (VDD). Therefore, two types of PCF8578 or PCF8579 can be distinguished on the same I2C-bus which allows: 1. One PCF8578 to operate with up to 32 PCF8579s on the same I2C-bus for very large applications (see Table 16). 2. The use of two types of LCD multiplex schemes on the same I2C-bus. In most applications the PCF8578 will have the same slave address as the PCF8579. The I2C-bus protocol is shown in Figure 13. All communications are initiated with a START condition (S) from the I2C-bus master, which is followed by the desired slave address and read/write bit. All devices with this slave address acknowledge in parallel. All other devices ignore the bus transfer. In WRITE mode (indicated by setting the read/write bit LOW) one or more commands follow the slave address acknowledgement. The commands are also acknowledged by all addressed devices on the bus. The last command must clear the continuation bit C. After the last command a series of data bytes may follow. The acknowledgement after each byte is made only by the (A0, A1, A2 and A3) addressed PCF8579 or PCF8578 with its implicit subaddress 0. After the last data byte has been acknowledged, the I2C-bus master issues a STOP condition (P). In READ mode, indicated by setting the read/write bit HIGH, data bytes may be read from the RAM following the slave address acknowledgement. After this acknowledgement the master transmitter becomes a master receiver and the PCF8579 becomes a slave transmitter. The master receiver must acknowledge the reception of each byte in turn. The master receiver must signal an end of data to the slave transmitter, by not generating an acknowledge on the last byte clocked out of the slave. The slave transmitter then leaves the data line HIGH, enabling the master to generate a STOP condition (P). Display bytes are written into, or read from the RAM at the address specified by the data pointer and subaddress counter. Both the data pointer and subaddress counter are automatically incremented, enabling a stream of data to be transferred either to, or from the intended devices.
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
15 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
In multiple device applications, the hardware subaddress pins of the PCF8579s (A0 to A3) are connected to VSS or VDD to represent the desired hardware subaddress code. If two or more devices share the same slave address, then each device must be allocated a unique hardware subaddress.
R/ W slave address
acknowledge by all addressed PCF8578s / PCF8579s
acknowledge by A0, A1, A2 and A3 selected PCF8578s / PCF8579s only
S
S 0 1 1 1 1 0A 0AC 0 1 byte
COMMAND
A
DISPLAY DATA
A
P
n 0 byte(s)
n 0 byte(s) update data pointers and if necessary, subaddress counter
msa830
(a)
a. Master transmits to slave receiver (write mode)
acknowledge by all addressed PCF8578s / PCF8579s slave address S 0 1 1 1 1 0 A 0 AC 0 R/ W AS slave address S 011110A1A 0 acknowledge from master no acknowledge from master
S
COMMAND n 1 byte
DATA
A
DATA
1
P
R/W at this moment master transmitter becomes a master receiver and PCF8578/PCF8579 slave receiver becomes a slave transmitter (b)
n bytes
last byte update data pointers and if necessary subaddress counter
msa832
b. Master reads after sending command string (write commands; read data)
acknowledge by all addressed PCF8578s / PCF8579s slave address S 011110A1A 0
acknowledge from master
no acknowledge from master
S
DATA
A
DATA
1
P
R/ W
n bytes
last byte update data pointers and if necessary, subaddress counter
msa831
(c)
c. Master reads slave immediately after sending slave address (read mode) Fig 13. I2C-bus protocol
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
16 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
8.7 Display RAM
The PCF8579 contains a 32 x 40-bit static RAM which stores the display data. The RAM is divided into 4 banks of 40 bytes (4 x 8 x 40 bits). During RAM access, data is transferred to or from the RAM via the I2C-bus.
8.7.1 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This allows an individual data byte or a series of data bytes to be written into, or read from, the display RAM, controlled by commands sent on the I2C-bus.
8.7.2 Subaddress counter
The storage and retrieval of display data is dependent on the content of the subaddress counter. Storage and retrieval take place only when the contents of the subaddress counter matches with the hardware subaddress at pins A0, A1, A2 and A3.
8.8 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. The five commands available to the PCF8579 are defined in Table 6.
Table 6. Command Bit set-mode set-start-bank device-select RAM-access load-X-address Definition of PCF8579 commands Operation code 7 C C C C C 6 1 1 1 1 0 5 0 1 1 1 X[5:0] 4 T 1 0 1 3 E[1:0] 1 A[3:0] G[1:0] Y[1:0] 1 2 1 M[1:0] B[1:0] 0 Table 8 Table 9 Table 10 Table 11 Table 12 Reference
The most-significant bit of a command is the continuation bit C (see Table 7 and Figure 14). Commands are transferred in WRITE mode only.
Table 7. Bit 7 C bit description Symbol C 0 1 Value Description continue bit last control byte in the transfer; next byte will be regarded as display data control bytes continue; next byte will be a command too
MSB C REST OF OPCODE
LSB
msa833
C = 0; last command. C = 1; commands continue.
Fig 14. General information of command byte
PCF8579_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
17 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
Set-mode - command bit description Symbol C T 0 1 Value 0, 1 10 Description see Table 7 fixed value display mode PCF8578 row only PCF8578 mixed mode display status 00 01 10 11 blank normal all segments on inverse video LCD drive mode 01 10 11 00 1:8 MUX (8 rows) 1:16 MUX (16 rows) 1:24 MUX (24 rows) 1:32 MUX (32 rows)
Table 8. Bit 7 6, 5 4
3, 2
E[1:0]
1, 0
M[1:0]
Table 9. Bit 7 6 to 2 1, 0
Set-start-bank - command bit description Symbol C B[1:0] 00 01 10 11 Value 0, 1 11111 Description see Table 7 fixed value start bank pointer (see Figure 18)[1] bank 0 bank 1 bank 2 bank 3
[1]
Useful for scrolling, pseudo-motion and background preparation of new display content.
Table 10. Bit 7 6 to 4 3 to 0
Device-select - command bit description Symbol C A[3:0] Value 0, 1 110 0 to 15[1] Description see Table 7 fixed value hardware subaddress; 4 bit binary value; transferred to the subaddress counter to define one of sixteen hardware subaddresses
[1]
Values shown in decimal.
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
18 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
RAM-access - command bit description Symbol C G[1:0] Value 0, 1 111 Description see Table 7 fixed value RAM access mode; defines the auto-increment behavior of the address for RAM access (see Figure 17) 00 01 10 11 character half-graphic full-graphic not allowed[1] RAM row address; two bits of immediate data, transferred to the Y-address pointer to define one of four display RAM rows (see Figure 15)
Table 11. Bit 7 6 to 4 3, 2
1, 0
Y[1:0]
0 to 3[2]
[1] [2]
See operation code for set-start-bank in Table 9. Values shown in decimal.
Table 12. Bit 7 6 5 to 0
Load-X-address - command bit description Symbol C X[5:0] Value 0, 1 0 0 to 39[1] Description see Table 7 fixed value RAM column address; six bits of immediate data, transferred to the X-address pointer to define one of forty display RAM columns (see Figure 15)
[1]
Values shown in decimal.
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
19 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
8.9 RAM access
1 byte 0 LSB Y address Y max
MSB
0
X address
X max
001aaj920
Fig 15. RAM addressing scheme
There are three RAM-access modes:
* Character * Half-graphic * Full-graphic
These modes are specified by the bits G[1:0] of the RAM-access command. The RAM-access command controls the order in which data is written to or read from the RAM (see Figure 17). To store RAM data, the user specifies the location into which the first byte will be loaded (see Figure 16):
* Device subaddress (specified by the device-select command) * RAM X-address (specified by the bits X[5:0] of the load-X-address command) * RAM bank (specified by the bits Y[1:0] of the RAM-access command)
Subsequent data bytes will be written or read according to the chosen RAM-access mode. Device subaddresses are automatically incremented between devices until the last device is reached. If the last device has subaddress 15, further display data transfers will lead to a wrap-around of the subaddress to 0.
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
20 of 41
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Product data sheet Rev. 05 -- 11 May 2009
S
(c) NXP B.V. 2009. All rights reserved. PCF8579_5
NXP Semiconductors
DEVICE SELECT: subaddress 12 RAM ACCESS: character mode bank 1 RAM bank 0 bank 1 bank 2 bank 3
LOAD X-ADDRESS: X-address = 8 R/ W slave address READ R /W slave address DEVICE SELECT LOAD X-ADDRESS RAM ACCESS S S 011110A1A 0 DATA
A
LCD column driver for dot matrix graphic displays
S 011110A0A11101100A10001000A01110001A 0 last command DATA A DATA A
msa835
WRITE
PCF8579
21 of 41
Fig 16. Example of commands specifying initial data byte RAM locations
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Product data sheet Rev. 05 -- 11 May 2009
(c) NXP B.V. 2009. All rights reserved. PCF8579_5
NXP Semiconductors
PCF8578/PCF8579
driver 1
PCF8579
driver 2 driver k
bank 0 bank 1 bank 2 bank 3 PCF8578/PCF8579 system RAM 1 k 16 LSB
RAM 4 bytes
40-bits
1 byte
0
1
2
3
4
5
6
7
8
9 10 11 character mode MSB
LCD column driver for dot matrix graphic displays
0 2 bytes 1
2 3
4 5
6 7
8 10 12 14 16 18 20 22 9 11 13 15 17 19 21 23 half-graphic mode
0 1 4 bytes 2 3
4 5
8 12 16 20 24 28 32 36 40 44 9 13 17 21 25 29 33 37 41 45
6 10 14 18 22 26 30 34 38 42 46 7 11 15 19 23 27 31 35 39 43 47 RAM data bytes are written or read as indicated above full-graphic mode
msa849
PCF8579
22 of 41
Fig 17. RAM access mode
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
8.9.1 Display control
The display is generated by continuously shifting rows of RAM data to the dot matrix LCD via the column outputs. The number of rows scanned depends on the multiplex rate set by bits M[1:0] of the set-mode command.
RAM bank 0 top of LCD
bank 1
LCD
bank 2
bank 3
msa851
1:32 multiplex rate and start bank = 2.
Fig 18. Relationship between display and set-start-bank
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
23 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
The display status (all dots on or off and normal or inverse video) is set by the bits E[1:0] of the set-mode command. For bank switching, the RAM bank corresponding to the top of the display is set by the bits B[1:0] of the set-start-bank command. This is shown in Figure 18. This feature is useful when scrolling in alphanumeric applications.
9. Limiting values
Table 13. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VLCD VI Parameter supply voltage LCD supply voltage input voltage VDD related; on pins SDA, SCL, CLK, TEST, SA0 and OSC VLCD related; V3 and V4 VO output voltage VDD related; SYNC and CLK VLCD related; R0 to R7, R8/C8 to R31/C31 and C32 to C39 II IO IDD IDD(LCD) ISS Ptot Po Tstg
[1]
Conditions
Min -0.5 VDD - 11 -0.5
Max +8.0 +8.0 +8.0
Unit V V V
VDD - 11 -0.5 VDD - 11
+8.0 +8.0 +8.0
V V V
input current output current supply current LCD supply current ground supply current total power dissipation output power storage temperature
[1]
-10 -10 -50 -50 -50 per package -65
+10 +10 +50 +50 +50 400 100 +150
mA mA mA mA mA mW mW C
According to the NXP store and transport conditions (document SNW-SQ-623) the devices have to be stored at a temperature of +5 C to +45 C and a humidity of 25 % to 75 %.
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
24 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
10. Static characteristics
Table 14. Static characteristics VDD = 2.5 V to 6 V; VSS = 0 V; VLCD = VDD - 3.5 V to VDD - 9 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Supplies VDD VLCD IDD VPOR Logic VIL VIH IL LOW-level input voltage HIGH-level input voltage leakage current at pins SDA, SCL, SYNC, CLK, TEST and SA0, A0 to A3; Vi = VDD or VSS at pin SDA; VOL = 0.4 V; VDD = 5 V at pin SCL and SDA at pins V3 and V4; Vi = VDD or VLCD on pins C0 to C39 on pins at C0 to C39
[4] [3]
Parameter supply voltage LCD supply voltage supply current power-on reset voltage
Conditions
Min 2.5 VDD - 9
Typ 9 1.3 -
Max 6.0 VDD - 3.5 20 1.8 0.3VDD VDD +1
Unit V V A V V V mA
fclk = 2 kHz
[1] [2]
VSS 0.7VDD -1
IOL
LOW-level output current
3
-
-
mA
Ci IL Voffset(DC) RO
[1] [2] [3] [4]
input capacitance leakage current DC offset voltage output resistance
-2 -
20 3
5 +2 6
pF A mV k
LCD outputs
Outputs are open; inputs at VDD or VSS; I2C-bus inactive; external clock with 50 % duty factor. Resets all logic when VDD < VPOR. Periodically sampled; not 100 % tested. Resistance measured between output terminal (C0 to C39) and bias input (V3, V4, VDD and VLCD) when the specified current flows through one output under the following conditions (see Table 4): a) Voper = VDD - VLCD = 9 V. b) V3 - VLCD 4.70 V; V4 - VLCD 4.30 V; Iload = 100 A.
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
25 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
11. Dynamic characteristics
Table 15. Dynamic characteristics All timing values are referenced to VIH and VIL levels with an input voltage swing of VSS to VDD. VDD = 2.5 V to 6 V; VSS = 0 V; VLCD = VDD - 3.5 V to VDD - 9 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol fclk tPD(drv) I2C-bus fSCL tw(spike) tBUF tSU;STA tHD;STA tLOW tHIGH tr tf tSU;DAT tHD;DAT tSU;STO
[1]
Parameter clock frequency driver propagation delay
Conditions 50 % duty factor VDD - VLCD = 9 V; with test load of 45 pF
[1]
Min -
Typ -
Max 10 100
Unit kHz s
SCL clock frequency spike pulse width bus free time between a STOP and START condition set-up time for a repeated START condition hold time (repeated) START condition LOW period of the SCL clock HIGH period of the SCL clock rise time of both SDA and SCL signals fall time of both SDA and SCL signals data set-up time data hold time set-up time for STOP condition
4.7 4.7 4.0 4.7 4.0 250 0 4.0
-
100 100 1 0.3 -
kHz ns s s s s s s s ns ns s
Typically 0.9 kHz to 3.3 kHz.
0.7 V 0. V
0. V 0 V -V V 0. V
013aaa031
Fig 19. Driver timing waveforms
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
26 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
SDA
tBUF
tLOW
tf
SCL
tHD;STA
tr
tHD;DAT
tHIGH
tSU;DAT
SDA
tSU;STA tSU;STO
mga728
Fig 20. I2C-bus timing waveforms
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
27 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
12. Application information
Large display configurations of one PCF8578 and up to 32 PCF8579 can be recognized on the same I2C-bus by using the 4-bit hardware subaddress A[3:0] and the I2C-bus slave address SA0.
Table 16. Example of addressing one PCF8578 and 32 PCF8579 Pins connected to VSS are logic 0; pins connected to VDD are logic 1. Cluster PCF8578 PCF8579 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
PCF8579_5
SA0 0
A3 -
A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Device 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
28 of 41
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Product data sheet Rev. 05 -- 11 May 2009
(c) NXP B.V. 2009. All rights reserved. PCF8579_5
NXP Semiconductors
VDD VDD
C C C C C R
32 V2 rows LCD DISPLAY
R
1:32 multiplex rate 32 x 40 x k dots (k 16) (20480 dots max.)
V3
(4 2 3)R 8
V4
R
PCF8578
(ROW MODE)
unused columns VDD VDD VLCD
40 columns A0 #1 A1 A2
subaddress 0 VDD VDD VLCD V3
40 columns A0 #2 A1 A2
subaddress 1 VDD VDD VLCD V3
40 columns
subaddress k-1 A0
V5
R
SA0 VLCD
VSS
#k
A1 A2
VLCD
VSS
OSC
V3
Rext(OSC)
PCF8579
PCF8579
PCF8579
VSS SDA SCL CLK SYNC VSS VDD
V4 A3 VSS SYNC CLK SCL SDA SA0
VSS VSS
V4 A3 VSS SYNC CLK SCL SDA SA0 VSS VSS
V4 A3 VSS SYNC CLK SCL SDA SA0
LCD column driver for dot matrix graphic displays
VSS
VSS
SCL SDA
msa845
PCF8579
Fig 21. Typical LCD driver system with 1:32 multiplex rate
29 of 41
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Product data sheet Rev. 05 -- 11 May 2009
VDD SCL SDA
msa847
PCF8579_5
VDD VSS VDD VSS VDD VSS SA0 SDA SCL CLK SYNC VSS V3 A3 A2 A1 A0 40 columns #k V4 VLCD VDD VDD SA0 SDA SCL CLK SYNC VSS V3 A3 A2 A1 A0 40 columns 1:16 multiplex rate 16 x 40 x k dots (k 16) (10240 dots max.) 1:16 multiplex rate 16 x 40 x k dots (k 16) (10240 dots max.) #2 V4 VLCD VDD VDD SA0 SDA SCL CLK SYNC VSS A3 V3 A2 A1 A0 40 columns #1 V4 VLCD VDD VDD
NXP Semiconductors
PCF8579
PCF8579
PCF8579
subaddress k 1 VDD VDD
C R
subaddress 1
subaddress 0
16 rows LCD DISPLAY
V2
C R
16 rows
V3
C R
LCD column driver for dot matrix graphic displays
V4
C R
PCF8578
(ROW MODE)
8 unused columns VDD VSS/VDD VDD VLCD V3 #1
40 columns
subaddress 0 VDD VDD VLCD V3 V4 VSS VSS #2
40 columns
subaddress 1 VDD VDD VLCD V3 V4 VSS VSS #k
40 columns
subaddress k 1
V5
C R
SA0 VLCD
A0 A1 A2 A3 SYNC CLK SCL SDA SA0 VSS
A0 A1 A2 A3 SYNC CLK SCL SDA SA0 VSS
A0 A1 A2 A3 SYNC CLK SCL SDA SA0 VSS
VLCD
PCF8579
PCF8579
PCF8579
VSS
OSC
Rext(OSC)
V4 VSS VSS
VSS SDA SCL CLK SYNC
VSS
PCF8579
(c) NXP B.V. 2009. All rights reserved.
30 of 41
Fig 22. Split screen application with 1:16 multiplex rate for improved contrast
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Product data sheet Rev. 05 -- 11 May 2009
VDD SCL SDA
msa846
PCF8579_5
VDD VSS VDD VSS VDD VSS SA0 SDA SCL CLK SYNC VSS A3 A2 A1 A0 40 columns #k V3 V4 VLCD VDD VDD SA0 SDA SCL CLK SYNC VSS A3 A2 A1 A0 40 columns 1:32 multiplex rate 32 x 40 x k dots (k 16) (20480 dots max.) 32 32 rows 1:32 multiplex rate 32 x 40 x k dots (k 16) (20480 dots max.) #2 V3 V4 VLCD VDD VDD SA0 SDA SCL CLK SYNC VSS A3 A2 A1 A0 40 columns #1 V3 V4 VLCD VDD VDD
NXP Semiconductors
PCF8579
PCF8579
PCF8579
subaddress k 1 VDD VDD
C R
subaddress 1
subaddress 0
LCD DISPLAY
V2
C R (4 2 3)R
V3
C
LCD column driver for dot matrix graphic displays
V4
C R
PCF8578
(ROW MODE)
8 unused columns VDD VSS/VDD VDD VLCD V3 #1
40 columns
subaddress 0 VDD VDD VLCD V3 V4 #2
40 columns
subaddress 1 VDD VDD VLCD V3 V4 #k
40 columns
subaddress k 1
V5
C R
SA0 VLCD
A0 A1 A2 A3 SCL SDA SA0 VSS
A0 A1 A2 A3
A0 A1 A2
VLCD
PCF8579
PCF8579
PCF8579
VSS VSS
OSC
Rext(OSC)
V4 VSS SYNC CLK VSS
SDA SCL CLK SYNC
VSS SYNC CLK SCL SDA SA0 VSS VSS
A3 VSS SYNC CLK SCL SDA SA0 VSS VSS
VSS
PCF8579
(c) NXP B.V. 2009. All rights reserved.
31 of 41
Fig 23. Split screen application with 1:32 multiplex rate
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Product data sheet Rev. 05 -- 11 May 2009
(c) NXP B.V. 2009. All rights reserved. PCF8579_5
NXP Semiconductors
VSS SCL VDD VLCD SDA
R0
R
Rext(OSC) (4 2 3)R RR R
n.c. n.c.
LCD DISPLAY
PCF8578
R31/C31 C0 C27 C28 C39 C0 C27 C28 C39
LCD column driver for dot matrix graphic displays
PCF8579
PCF8579
Fig 24. Example of single plane wiring, single screen with 1:32 multiplex rate (PCF8578 in row driver mode)
n. c.
n. c.
to other PCF8579s
msa852
PCF8579
32 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
13. Package outline
VSO56: plastic very small outline package; 56 leads SOT190-1
D
E
A X
c y HE vM A
Z 56 29
Q A2 A1 pin 1 index Lp L 1 e bp 28 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 3.3 0.13 A1 0.3 0.1 0.012 0.004 A2 3.0 2.8 0.12 0.11 A3 0.25 0.01 bp 0.42 0.30 c 0.22 0.14 D (1) 21.65 21.35 E (2) 11.1 11.0 e 0.75 HE 15.8 15.2 L 2.25 0.089 Lp 1.6 1.4 0.063 0.055 Q 1.45 1.30 v 0.2 w 0.1 y 0.1 Z (1) 0.90 0.55
0.017 0.0087 0.85 0.012 0.0055 0.84
0.44 0.62 0.0295 0.43 0.60
0.057 0.035 0.008 0.004 0.004 0.051 0.022
7o o 0
Notes 1. Plastic or metal protrusions of 0.3 mm (0.012 inch) maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT190-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 97-08-11 03-02-19
Fig 25. Package outline of PCF8579T/1 (VSO56)
PCF8579_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
33 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
c
y X A 48 49 33 32 ZE
e E HE wM bp 64 1 pin 1 index 16 ZD bp D HD wM B vM B vM A 17 detail X L Lp A A2 A1 (A 3)
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7o o 0
12.15 12.15 11.85 11.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT314-2 REFERENCES IEC 136E10 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Fig 26. Package outline PCF8579H/1 (LQFP64)
PCF8579_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
34 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
TQFP64: plastic thin quad flat package; 64 leads; body 10 x 10 x 1.0 mm
SOT357-1
c
y X A 48 49 33 32 ZE
e E HE A wM pin 1 index bp 17 1 16 ZD bp D HD wM B vM B vM A detail X Lp L A2 A 1 (A 3)
64
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.1 Z D(1) Z E(1) 1.45 1.05 1.45 1.05 7 o 0
o
12.15 12.15 11.85 11.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT357-1 REFERENCES IEC 137E10 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 02-03-14
Fig 27. Package outline PCF8579HT/1 (TQFP64)
PCF8579_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
35 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
PCF8579_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
36 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
14.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 28) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 17 and 18
Table 17. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 18. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 28.
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
37 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 28. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
15. Abbreviations
Table 19. Acronym CMOS DC I2C IC LCD LSB MSB MSL PCB POR RC RAM RMS SCL SDA SMD Abbreviations Description Complementary Metal Oxide Semiconductor Direct Current Inter-Integrated Circuit Integrated Circuit Liquid Crystal Display Least Significant Bit Most Significant Bit Moisture Sensitivity Level Printed-Circuit Board Power-On Reset Resistance-Capacitance Random Access Memory Root Mean Square Serial Clock Line Serial Data Line Surface Mount Device
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
38 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
16. Revision history
Table 20. Revision history Release date 20090511 Data sheet status Product data sheet Change notice Supersedes PCF8579_4 Document ID PCF8579_5 Modifications:
* * * * * * * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added package type TQFP64 Removed bare die types Rearranged information in data sheet Changed letter symbols to NXP approved symbols Added RAM addressing scheme (Figure 15) Added addressing example (Table 16) Product data sheet Product data sheet Product data sheet Product data sheet PCF8579_3 PCF8579_2 PCF8579_1 -
PCF8579_4 PCF8579_3 PCF8579_2 PCF8579_1
20030901 19970401 19961025 19940125
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
39 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PCF8579_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 11 May 2009
40 of 41
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
19. Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 8.6.6 8.6.7 8.7 8.7.1 8.7.2 8.8 8.9 8.9.1 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . . 7 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 7 Multiplexed LCD bias generation . . . . . . . . . . . 8 LCD drive mode waveforms . . . . . . . . . . . . . . 10 Timing generator. . . . . . . . . . . . . . . . . . . . . . . 13 Column drivers . . . . . . . . . . . . . . . . . . . . . . . . 13 Characteristics of the I2C-bus . . . . . . . . . . . . . 13 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 START and STOP conditions . . . . . . . . . . . . . 13 System configuration . . . . . . . . . . . . . . . . . . . 13 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 13 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 15 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 15 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Subaddress counter . . . . . . . . . . . . . . . . . . . . 17 Command decoder . . . . . . . . . . . . . . . . . . . . . 17 RAM access . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Display control . . . . . . . . . . . . . . . . . . . . . . . . 23 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 24 Static characteristics. . . . . . . . . . . . . . . . . . . . 25 Dynamic characteristics . . . . . . . . . . . . . . . . . 26 Application information. . . . . . . . . . . . . . . . . . 28 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 33 Soldering of SMD packages . . . . . . . . . . . . . . 36 Introduction to soldering . . . . . . . . . . . . . . . . . 36 Wave and reflow soldering . . . . . . . . . . . . . . . 36 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 36 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 37 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 39 Legal information. . . . . . . . . . . . . . . . . . . . . . . 40 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 40 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 17.4 18 19 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Contact information . . . . . . . . . . . . . . . . . . . . 40 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 May 2009 Document identifier: PCF8579_5

▲Up To Search▲

Price & Availability of PCF8579T1

	To Download PCF8579T1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .